Exemplary embodiments relate to a nonvolatile memory device and, more particularly, to a page buffer circuit, a nonvolatile memory device including the page buffer circuit, and a method of operating the nonvolatile memory device, which are capable of reducing a peak current according to the recovery of a bit line voltage by controlling the bit line voltage.
There is an increasing demand for semiconductor memory devices which can be electrically programmed and erased and can retain data even without the supply of power. To develop high-capacity memory devices capable of storing a large amount of data, technology for high-integrated memory cells is being developed. To this end, there was proposed a NAND type flash memory device in which a plurality of memory cells is coupled in series to form a string and a plurality of strings constitutes a memory cell array.
Each of the flash memory cells of the NAND type flash memory device includes a current path, formed between the source and the drain over a semiconductor substrate, and a floating gate and a control gate, formed between insulating layers over the semiconductor substrate. Furthermore, the program operation of the memory cell is mainly performed by grounding the source/drain regions of the memory cell and the semiconductor substrate (i.e., a bulk region) and supplying a high positive voltage to the control gate so that Fowler-Nordheim (F-N) tunneling is generated between the floating gate and the semiconductor substrate. Through such F-N tunneling, an electric field of the high voltage supplied to the control gate causes the electrons of the bulk region to be accumulated in the floating gate, thereby raising a threshold voltage of the memory cell.
Recently, to further increase the degree of integration of the flash memory cells, active research is being carried out on a multi-bit cell which is able to store plural data in one memory cell. This type of a memory cell is mainly referred to as a multi-level cell (MLC). A memory cell capable of storing a single bit is referred to as a single level cell (SLC).
FIG. 1A is a diagram showing a state in which a memory cell array and a page buffer are interconnected.
FIG. 1A illustrates a nonvolatile memory device, including a page buffer 120 and memory cells coupled to a pair of bit lines included in a memory cell array 110.
The pair of bit lines include an even bit line BLe and an odd bit line BLo. A cell string is coupled to each of the bit lines.
Each cell string includes a plurality of memory cells coupled in series between a drain select transistor and a source select transistor.
The gates of the memory cells are respectively coupled to 0th to thirty-first word lines WL<0> to WL<31>. A drain selection line DSL is coupled to the gates of the drain select transistors of each of the cell strings, and a source selection line SSL is coupled to the gates of the source select transistors of each of the cell strings. The sources of the source select transistors are coupled to a global source line GL.
The page buffer unit 120 includes a bit line selection unit 121, a sense unit 122, a precharge unit 123, and a plurality of latch units 124.
The bit line selection unit 121 couples the sense unit 122 and a bit line which is selected when a program or read operation is performed. The bit line selection unit 121 precharges or discharges the selected bit line.
The sense unit 122 senses voltage of a bit line coupled thereto and changes the voltage level of a sense node SO. The precharge unit 123 precharges the sense node SO. The plurality of latch units 124 transfer program data to the sense node SO or latch data according to the voltage level of the sense node SO.
The bit line selection unit 121 selects the even bit line BLe or the odd bit line no. A variable voltage VIRPWR for precharging or discharging a selected bit line is supplied to the bit line selection unit 121. The variable voltage VIRPWR is generated by a variable voltage generator (not shown). The variable voltage generator generates and supplies the variable voltage VIRPWR in order to recover a voltage drop when voltage of a precharged bit line drops.
FIG. 1B is a circuit diagram of the variable voltage generator for supplying the variable voltage shown in FIG. 1A.
Referring to FIG. 1B, the variable voltage generator 125 includes a comparator COM and first to third PMOS transistors MP1 to MP3.
The comparator COM has an inverting terminal (−) to which a reference variable voltage VIRPWR_REF is inputted. The first to third PMOS transistors MP1 to MP3 are coupled in series between a power source voltage Vcc and a ground node Vss. The gate of the second PMOS transistor MP2 is coupled to the non-inverting terminal (+) of the comparator COM.
The variable voltage VIRPWR is outputted from a node of the first PMOS transistor MP1 and the second PMOS transistor MP2.
A process of setting the voltage of a bit line when a program operation is performed is described below with reference to FIGS. 1A and 1B.
To perform a program operation, the even and odd bit lines BLe, BLo are precharged by the variable voltage VIRPWR.
In the case in which the even bit line BLe is selected, the even bit line BLe is maintained at the precharge state or discharged in response to a data state of one of the latch units 124 in which program data are stored.
In the case in which the even bit line BLe is discharged, the voltage level of the odd bit line BLo drops because of a coupling effect. Thus, a peak current is generated due to such a sudden voltage drop. The variable voltage generator 125 performs a recovery operation for sensing the voltage drop of the odd bit line BLo and recovering the voltage level of the odd bit line BLo.
In the structure in which a program operation is alternately performed on the even bit line BLe and the odd bit line BLo, problems, such as a voltage drop and a peak current, are inevitably generated because of a change in the voltage of a selected bit line occurring in response to a state of program data.